6 hours

Staff Signal Integrity and Power Integrity Engineer

  • Job Code
Job Title: Staff Signal Integrity and Power Integrity Engineer 153836

Primary Location Singapore-Singapore-Singapore
Job: Design Engineering
Schedule: Full-time

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for smart, collaborative, creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community. We are ONEXILINX.


Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx’s all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide.  For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science—from the industry’s first fabless semiconductor model to the NASA Curiosity Mars Rover, to today’s autonomous vehicles and hyperscale data centers.  Xilinx uniquely enables applications that are both software-defined, yet hardware optimized – enabling smart, connected and differentiated applications across technology’s biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more. 


We are looking for a signal integrity engineer to design and analyze high speed interfaces and power distribution network. The candidate will work with other related design teams to define and design the product to meet power and high speed I/O requirements and help the lab measurement and debug. 
Detailed responsibilities are listed below:
1)  Power integrity analysis, which includes but not limited to layout extraction, HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.
2)  Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain.  Eye diagram and jitter analysis via Chip-package-board co-simulation.
3)  Optimal layer stackup & VDD/VSS plane/island assignment to minimize voltage drop/noise/coupling.
4)  Special noise-sensitive power supply analysis and layout guideline.
5)  Signal trace length variation/matching and impact to timing.
6)  Crosstalk analysis and reduction.
7)  Insertion loss and return loss modeling and improvement with HFSS. #hot



The successful incumbent should be/possess the following attributes:
  • Master of Science degree in Electrical & Electronics Engineering with 3-5 years experience or PhD
  • Solid background on transmission line theory and in depth knowledge of electromagnetics.
  • Experience with HSPICE, HFSS, Q3D, PowerSI, and Agilent ADS.
  • Experience with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers.
  • Self motivated, teamwork, and good communication skills.

Job Posting: Jul 18, 2017, 2:38:31 AM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to age, race, gender, religion, marital status and family responsibilities, disability or sexual orientation.


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