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Staff Signal Integrity and Power Integrity Engineer

  • Job Code
Job Title: Staff Signal Integrity and Power Integrity Engineer 153836

Primary Location Singapore-Singapore-Singapore
Job: Design Engineering
Schedule: Full-time

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 


We are looking for a signal integrity engineer to design and analyze high speed interfaces and power distribution network. The candidate will work with other related design teams to define and design the product to meet power and high speed I/O requirements and help the lab measurement and debug. 
Detailed responsibilities are listed below:
1)  Power integrity analysis, which includes but not limited to layout extraction, HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.
2)  Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain.  Eye diagram and jitter analysis via Chip-package-board co-simulation.
3)  Optimal layer stackup & VDD/VSS plane/island assignment to minimize voltage drop/noise/coupling.
4)  Special noise-sensitive power supply analysis and layout guideline.
5)  Signal trace length variation/matching and impact to timing.
6)  Crosstalk analysis and reduction.
7)  Insertion loss and return loss modeling and improvement with HFSS. #hot



The successful incumbent should be/possess the following attributes:
  • Master of Science degree in Electrical & Electronics Engineering with 3-5 years experience or PhD
  • Solid background on transmission line theory and in depth knowledge of electromagnetics.
  • Experience with HSPICE, HFSS, Q3D, PowerSI, and Agilent ADS.
  • Experience with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers.
  • Self motivated, teamwork, and good communication skills.

Job Posting: Jul 17, 2017, 11:38:31 PM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to age, race, gender, religion, marital status and family responsibilities, disability or sexual orientation.


Posted: 2018-12-10 Expires: 2019-01-09

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